The 555 in figure 9 is shown here in it's almost basic mode of operation; as a triggered monostable.
One immediate observation is the extreme simplicity of this circuit. Only two components to make up a timer, a capacitor and a resistor. And for noise immunity maybe a capacitor on pin 5.
Due to the internal latching mechanism of the 555, the timer will always time-out once triggered, regardless of any subsequent noise (such as bounce) on the input trigger (pin 2). This is a great asset in interfacing the 555 with noisy sources. Just in case you do not know what 'bounce' is: bounce is a type of fast, short term noise caused by a switch, relay, etc. and then picked up by the input pin.
The trigger input is initially high (about 1/3 of +V). When a negative-going trigger pulse is applied to the trigger input (see fig. 9a), the threshold on the lower comparator is exceeded. The lower comparator, therefore, sets the flip-flop. That causes T1 to cut off, acting as an open circuit. The setting of the flip-flop also causes a positive-going output level which is the beginning of the output timing pulse.
The capacitor now begins to charge through the external resistor. As soon as the charge on the capacitor equal 2/3 of the supply voltage, the upper comparator triggers and resets the control flip-flop. That terminates the output pulse which switches back to zero. At this time, T1 again conducts thereby discharging the capacitor. If a negative-going pulse is applied to the reset input while the output pulse is high, it will be terminated immediately as that pulse will reset the flip-flop.
Whenever a trigger pulse is applied to the input, the 555 will generate its single-duration output pulse. Depending upon the values of external resistance and capacitance used, the output timing pulse may be adjusted from approximately one millisecond to as high as on hundred seconds. For time intervals less than approximately 1-millisecond, it is recommended that standard logic one-shots designed for narrow pulses be used instead of a 555 timer. IC timers are normally used where long output pulses are required. In this applicaton, the duration of the output pulse in seconds is approximately equal to:
T = 1.1 x R x C (in seconds)
The output pulse width is defined by the above formula and with relatively few restrictions, timing components R(t) and C(t) can have a wide range of values. There is actually no theoretical upper limit on T (output pulse width), only practical ones. The lower limit is 10uS. You may consider the range of T to be 10uS to infinity, bounded only by R and C limits. Special R(t) and C(t) techniques allow for timing periods of days, weeks, and even months if so desired.
However, a reasonable lower limit for R(t) is in the order of about 10Kilo ohm, mainly from the standpoint of power economy. Although R(t) can be lower that 10K without harm, there is no need for this from the standpoint of achieving a short pulse width. A practical minimum for C(t) is about 95pF; below this the stray effects of capacitance become noticeable, limiting accuracy and predictability. Since it is obvious that the product of these two minimums yields a T that is less the 10uS, there is much flexibility in the selection of R(t) and C(t). Usually C(t) is selected first to minimize size (and expense); then R(t) is chosen.
The upper limit for R(t) is in the order of about 15 Mega ohm but should be less than this if all the accuracy of which the 555 is capacle is to be achieved. The absolute upper limit of R(t) is determined by the threshold current plus the discharge leakage when the operating voltage is +5 volt. For example, with a threshold plus leakage current of 120nA, this gives a maximum value of 14M for R(t) (very optimistic value). Also, if the C(t) leakage current is such that the sum of the threshold current and the leakage current is in excess of 120 nA the circuit will never time-out because the upper threshold voltage will not be reached. Therefore, it is good practice to select a value for R(t) so that, with a voltage drop of 1/3 V+ across it, the value should be 100 times more, if practical.
So, it should be obvious that the real limit to be placed on C(t) is its leakage, not it's capacitance value, since larger-value capacitors have higher leakages as a fact of life. Low-leakage types, like tantalum or NPO, are available and preferred for long timing periods. Sometimes input trigger source conditions can exist that will necessitate some type of signal conditioning to ensure compatibility with the triggering requirements of the 555. This can be achieved by adding another capacitor, one or two resistors and a small signal diode to the input to form a pulse differentiator to shorten the input trigger pulse to a width less than 10uS (in general, less than T). Their values and criterion are not critical; the main one is that the width of the resulting differentiated pulse (after C) should be less than the desired output pulse for the period of time it is below the 1/3 V+ trigger level.
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